1. Field
Apparatuses and methods consistent with exemplary embodiments of the inventive concept relate to a scan flip-flop, and more particularly, to a high-speed low-power scan flip-flop, an operating method thereof and data processing devices having the same.
2. Description of the Related Art
To design a high speed operation chip, designing a high speed flip-flop may be required. A related-art master-slave flip-flop is widely used due to its small size and low power consumption. However, using the master-slave flip-flop in the high-speed operating chip reaches a limit due to data-to-output latency. To improve the limit of the master-slave flip-flop, a pulse flip-flop or a semi-dynamic flip-flop is developed. However, a yield of a chip using the pulse flip-flop or the semi-dynamic flip-flop is not good because of unstable characteristics of a pulse, and it is not easy to integrate the pulse-flip-flop or the semi-dynamic flip-flop on the chip because of a long hold time.